In general, there is a desire to provide digital to analog converters having increased resolution whilst also maintaining good differential non-linearity and good integral non-linearity. Typically a digital to analog converter comprises a chain 2 of series connected resistors as shown in FIG. 1. In this example the chain comprises N resistors labelled R1 to RN. The chain extends between two terminals labelled “VREFGND” which is typically held at a ground voltage and “VREF” to which a reference voltage is applied. The resistor chain 2 forms a resistive divider such that, if the resistors are of equal size, then the voltage occurring between resistor R1 and R2 is   1  Nof the reference voltage, the voltage at the node formed between R2 and R3 is   2  Nof the reference voltage and so on. These voltages are designated VS(0) to VS(N) in FIG. 1. A selector system, generally designated 4 comprises a series of switches S0 to SN each associated with a respective one of the nodes. A control unit (not shown) receives a word which is to be converted to an analog voltage. The control unit decodes the word to select only one of the switches S0 to SN which is to be closed thereby connecting an appropriate node of the resistor chain 2 to the output node VOUT.
Several years ago digital to analog converters having 8-bit resolution were considered to be adequate. This required the formation of 28 (or more accurately 28−1) resistors, hence 255 resistors were required to make the resistor chain to provide a output ranging between   0  255and   255  255Vref inclusive. However, to provide an extra 4-bits of resolution to give a 12-bit converter means that the number of resistors in the resistor chain increases approximately 16 fold to 4095. This significantly increases the size of the digital to analog converter on the semiconductor die hence resulting in a much more expensive component. Provision of even higher resolution digital to analog converters becomes increasingly difficult.
It is known to provide sub-ranging converters in order to increase the resolution of the converter without paying such a heavy penalty in component count. An example of such a device is disclosed in U.S. Pat. No. 4,491,825 in which a resistor string digital to analog converter forming a primary converter is tapped, at adjacent taps to provide inputs to a further sub-ranging converter which is formed as an R2R ladder. This arrangement works well. However it is necessary to provide buffers between the primary converter and the sub-ranging converter and these buffers take up significant space on the silicon die and can introduce offset errors and other potential non-linearities. Other schemes are known, such as that described in U.S. Pat. No. 5,969,657 which is a dual string digital to analog converter in which the least significant bit string loads the most significant bit string in a code dependent manner. This means the changing the most significant bit code alters the loading on the most significant bit string and the voltage at the taps on the string.
A further arrangement is described in U.S. Pat. No. 5,396,245 which has a converter divided into a most significant bit (MSB) subword decoder and a least significant bit (LSB) subword decoder. The MSB decoder is formed as a tapped resistor string and the MSB word selects adjacent taps for output lines. These are provided to the LSB decoder which is fabricated as a multi-input operational amplifier. The individual inputs are selectively switchable to either of the two output lines from the MSB decoder in accordance with the LSB word. Whilst this circuit works effectively for a single digital to analog converter, it should be noted that the input stages of each opamp capacitively loads the most significant bit string and consequently an attempt to share the most significant bit string between multiple subword decoders (sub-ranging converters) results in cross talk between the digital to analog converters.